- 熟 C/C++
- 熟TCL, PERL或PYTHON者佳
影像處理工程師(Image Processing Engineer)
- Image / video processing for document image / Computer vision / object recognition / segmentation
- DSP programming for image processing algorithm
- embedded SoC programming for image processing pipeline
- C, Python or C++ programming skills.
- Familiar with embedded Linux System & RTOS.
- Experience on DSP and SIMD programming.
- Background in digital image processing and signal processing theory
- The knowledge and experience of Deep Learning / Neural Network is a plus
ASIC/SOC Design Engineer - Littleton
The primary responsibility will be RTL design including block/function definition, specification, design, simulation and unit level verification of digital functions. Design areas include image processing, artificial neural networks, memory/cache controllers, codecs, AMBA bus/bridge design, DMA controllers, and other industry standard interfaces. Develop detailed specifications and implement those functions in Verilog/SystemVerilog. Perform initial unit level testing of the RTL. Collaborate with DV team to verify the correctness of the design. Support all design integration activities including Lint, CDC, and synthesis. Occasionally work with physical design team on timing closure, physical, power, and logical issues.
- BSEE or MSEE and 5 or more years of experience in RTL design
- Experience with Verilog and SystemVerilog for synthesis and verification
- Knowledge of scripting languages including Python, Tcl, C/C++ and shell scripts
- Knowledge of digital design best practices
- Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, and gate level simulation
- User of Synopsys simulation and synthesis tools
- Good understanding of design verification (DV)
- Experience with hands-on lab verification
- Strong communication and interpersonal skills for working with global team
- Able to meet project milestones and deadlines